1. Field of the Invention
The present invention relates to a processor system, and, in particular, to a processor system for high speed execution of computations of data obtained from a microprocessor.
2. Description of the Prior Art
FIG. 1 illustrates a processor system 100 using a conventional arithmetic device 11 or a computing device. The arithmetic device 11 comprises an instruction register 12, an internal register 13, and an arithmetic unit 14. Specification for an operation to the arithmetic device 11 is input to the instruction register 12 from a processor 10 through an address bus 15.
FIG. 2 shows the configuration of an item of address data (hereinafter referred to as "address") which is transferred through the address bus 15.
The arithmetic device 11 is addressed with a predetermined address. The high order bits of the address are used as a selection field. The lower bits of the address are an operation code specifying the operations of the arithmetic device 11, and a first source operand (SRC1) together with a second source operand (SRC2)/destination field, specifying two operand addresses.
FIG. 3 shows the configuration of the internal register 13. The internal register 13 is made up from 16-bit registers of 32 items (R0 to R31). It can be used as a 32-bit register by combination of a pair of the 16-bit registers.
The internal register 13 outputs data to the arithmetic unit 14 and receives computed results from the arithmetic unit 14 according to the addresses specified by the two fields SRC1 and SRC2 in the instruction registers 12.
The arithmetic device 11 performs a special operation when the register R0 is designated in the first source operand SRC1. When the register R0 is specified by the source operand SRC1, in a load operation to the internal register 13, the data on the data bus 16 is input to a register in the internal register 13 specified by the SRC2/destination field. In a store operation, the content of the register in the internal register 13 specified by the SRC2/destination field is output to the data bus 16.
FIG. 4 is a timing chart for the case where the multiplication process between value loaded into the internal register 13 in the arithmetic device 11 and immediate value as multiplication data provided from the data bus 16.
When an operation code for the load operation, the register R1 as a destination, and the register R0 for first source operand SRC1 are set in the instruction register 12 to set a first source operand into the register R1 in the arithmetic device 11, the value output on the data bus 16 is stored in the register R1 (see "bus cycle 1" shown in FIG. 4).
When the immediate data is used as the second source operand SRC2, a code is specified which shows a multiplication process in tile operation code, the register R0 is set in the SRC1, and the register R2 is set in the SRC2/destination. Accordingly, the value stored in the register R1 by the bus cycle 1 and the immediate value supplied from the data bus 16 are input to the arithmetic unit 14 and multiplied together. The computed result is stored in the register R1 (see "bus cycle 2" shown, in FIG. 4).
Next, in the bus cycle 3, when the register R0 is set in the first source operand SRC1 and the register R1 is set in the second source operand SRC2/destination, the value from the register R1 is output to the data bus 16.
The above-mentioned calculations are performed as three "mov" instructions from the processor 10.
The three "mov" instructions are shown as follows: EQU mov r1, @ load EQU mov r2, @ mul EQU mov @ store, r3
where mov instruction has a first operand as a source and a second operand as a destination, and is an instruction to transmit data. The characters "r1", "r2", and "r3" indicate the internal registers in the processor 10. Also, "@ load" indicates an operation for loading the register R1 of the arithmetic device 11, "@ mul" indicates an operation for multiplying the contents of the register R1 to the immediate value, and "@ store" indicates an address specifying an operation for reading out the result of the multiplication from the register R1.
However, as shown in FIG. 4, when the immediate value is used as the operand, the conventional arithmetic device 11 uses the data bus 16 for both of writing of the operand and of reading of the result of the multiplication process through the data bus 16.
Accordingly, one bus cycle is required for each of the write operation of operand and the read operation of arithmetic result.
As outlined above, the conventional arithmetic device 11 and the processor system 100 using the conventional arithmetic device 11 have the drawback that the execution time for computation using the arithmetic device 11 is long.
Next, another example of a processor system according to prior art will be described.
Conventionally, there have been cases where a computing element is connected to a bus of a professor to improve the performance of a processor system.
For example, when the processor does not have a built-in multiplier, there have been cases where a multiplier is set on the bus of the processor so that multiplication is carried out at high speed. In a processor without a built-in multiplier, the multiplication is carried out as repeated additions. In this case, for a 16-bit multiplier it is necessary to perform a maximum of 16 additions. When one clock cycle is required for the addition of one bit, 16 clock cycles are required for the addition. Fpr example, when utilizing a multiplier for input control or the like, the number of multiplications is high so that high speed multiplication is necessary.
FIG. 5 is an example of a processor system with a conventional external computing circuit. An arithmetic element is a multiplier 120. The processor system comprises a processor 100, a bus controller 11, the multiplier 120, a source register 130, a source register 140, and a buffer 180. The processor 100 is operated synchronously with a basic clock cycle BCLK and a double-frequency clock cycle CLK. Hereinafter, the term "clock cycle" refers merely to one cycle of the basic clock cycle BCLK. Data for input to the multiplier 120 is obtained from the source registers 130 and 140. The results of multiplications are output to a data bus via the buffer 150.
In the conventional example shown in FIG. 5 multiplication source data is written into the source register 130 and the source register 140 during a write bus cycle of the processor 100. Then,the results of multiplication of the multiplier 120 is transferred to the processor 100 in a read bus cycle of the processor 100.
The source registers 130, 140, and the buffer 150 are designated by addresses, respectively. Accordingly, the bus controller 110 outputs control signals SW1, SW2, and MOE to the source registers 13 and 14 and the buffer 150 when the addresses on the address bus 501 provided by a bus cycle of the processor 10 are equal to that of the source registers 130 and 140 and the buffer 150.
In the source registers 130, 140 the data on the data bus is latched internally at the rising edge of the control signals SW1 and SW2 respectively and is provided to the multiplier.
In addition, the buffer 150 outputs the various multiplied results output from the multiplier on the data bus when the control signal M0E is active (low level).
FIG. 6 is a timing chart for multiplication on the conventional processor system illustrated in FIG. 5. The processor 100 outputs an address specifying the source register 130 on the address bus at a clock cycle 1, which is a write bus cycle, and outputs data set in the source register 130 on the data bus.
The bus controller 110 outputs the rising edge of the control signal SW1 to the source register 130 at suitable timing.
At the rising edge, the source register 130 outputs this data to the multiplier 120. At a clock cycle 2 other multiplied data is set in the source register 140 in the same manner.
At a clock cycle 3, which is a read bus cycle, the processor 100 outputs the address of the buffer 150 to the address bus 501. The bus controller 110 activates the control signal MOE. The buffer 150 outputs the output from the multiplier 120 on the data bus and the processor 100 internally reads this result.
The time elapsed from the point where the data is set in the source registers 130, 140 until the processor 100 reads the result of the multiplication is part of one clock cycle, therefore the multiplier 120 should complete the multiplication within this time. In this manner, with the system shown in the conventional example of FIG. 5, a minimum time of three clock cycles is required to execute one multiplication. When an actual program is written for a multiplication process, three instructions of the following type are used. Three or more clock cycles are required the multiplication process to execute these three instructions. EQU mov r1, @ src 130--adr (1) EQU mov r2, @ src 140--adr (2) EQU mov @ mul--adr, r3 (3)
A mov instruction has a first operand as a source and a second operand as a destination, and is an instruction to transmit data. r1, r2, and r3 are internal registers of the processor. @ src130--adr, @ src140--adr, and @ mul--adr show the addresses for accessing the source register 130, the source register 140, and the buffer 150 respectively.
The instruction (1) Writes a value from the internal register r1 of the processor 100 to the source register 130. The instruction (2) writes a value from the internal register r2 of the processor 100 to the source register 140. The instruction (3) reads the result of multiplication to the internal register r3.
Eight clocks are required for executing three instructions (1), (2), and (3) when the number of actual execution clocks which are required for instructions (1) and (2) which execute the write bus cycle is two.
In this manner, even though the multiplication speed of the multiplier 120 is only one clock cycle, it is at high speed, the instructions for setting the data and reading out the multiplication result are separate. The process time is long, therefore time for at least eight clock cycles is necessary for one multiplication.
As outlined above, in a conventional processor system, separate instructions must be provided when setting data from the processor into the multiplier and reading out the multiplication results, so considerable time is required. This has the drawback that a high speed process cannot be provided.